MT3620 Support Status

This document describes the current status of Azure Sphere support for the MediaTek MT3620. You may also want to refer to the MT3620 Product Brief, which is available for download on the MediaTek MT3620 web page. In addition, MediaTek produces the MT3620 Hardware User Guide, which is a detailed guide to integrating the MT3620 MCU into your own hardware.

If you have feature requests or feedback, we welcome your comments on the Azure Sphere community forum.

MT3620 block diagram

The block diagram shows the support provided for each MT3620 component. The sections that follow the diagram provide additional details about these components.

I/O peripherals

The MT3620 design includes a total of 76 programmable I/O pins. As shown in the following two tables, most of the pins are multiplexed between general-purpose I/O (GPIO) and other functions. In addition to the GPIO pins listed, GPIO12-23 are available on MT3620 pins 27-38 respectively.

Referring to the following table, pins marked "UNUSED" are not used by the associated ISU peripheral and can be configured for use as GPIO pins.

GPIO/PWM/counters

Some pins are multiplexed between GPIO, pulse width modulation (PWM), and hardware counters.

GPIO functions currently supported are setting output high/low and reading input. Open drain/open source driving modes and control of drive strength are also supported. External Interrupts are supported on the M4 core but not on the A7 core.

The MT3620 has 12 PWM channels, identified by PWM0-PWM11. They are organized into 3 groups of 4 channels. Each group is associated with a PWM controller (PWM-CONTROLLER-0, PWM-CONTROLLER-1, PWM-CONTROLLER-2). The PWM channels and GPIO pins GPIO0 through GPIO11 map to the same pins on the MT3620. If your application uses a PWM controller, all of the pins associated with that controller are allocated for use as PWM outputs and none of them can be used for GPIO.

The PWM hardware can be configured to use one of three fixed-clock frequencies: 32 KHz, 2 MHz (XTAL/13), or 26 MHz (XTAL). On the real-time (RT) cores, a real-time application (RTApp) can select which clock to use as the base. On the high-level core (A7), the Linux driver will always use the 2 MHz clock. This results in duty cycle and period limitations in high-level applications, as explained in Use PWMs in high-level applications.

Serial interface (ISU) blocks

The MT3620 design includes five serial interface blocks, each of which contains five pins. (These blocks are also called ISU, for "I2C, SPI, UART.") These serial interface blocks can multiplex GPIO, universal asynchronous receiver-transmitter (UART), inter-integrated circuit (I2C) and serial peripheral interface (SPI).

UART is supported at 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400, 460800, 500000, 576000, 921600, 1000000, 1152000, 1500000, and 2000000 baud. There is a 32-byte hardware receive buffer. The following UART settings are supported, with 8N1 (8 data bits, 1 stop bit, and no parity) as the default setting:

• Data bit: 5, 6, 7, and 8.
• Stop bit: 1 and 2.
• Parity: odd, even, and none.
• Flow control mode: RTS/CTS, XON/XOFF, and no flow control.

SPI transactions are supported up to 40 MHz. You can connect up to two subordinate SPI devices to each ISU. When you use an ISU port as an SPI master interface, you can't use the same port as an I2C or UART interface. Simultaneous bidirectional read and write (full-duplex) SPI operations within a single bus transaction are not supported. The following SPI settings are supported:

• Communication mode (clock polarity, clock phase): SPI mode 0 (CPOL = 0, CPHA = 0), SPI mode 1 (CPOL = 0, CPHA = 1), SPI mode 2 (CPOL = 1, CPHA = 0), and SPI mode 3 (CPOL = 1, CPHA = 1).
• Bit order: least significant is sent first, and most significant is sent first.
• Chip select polarity: active-high, active-low. Active-low is the default setting.

7-bit subordinate device addresses are supported for I2C. 8-bit or 10-bit I2C subordinate addresses are not supported. When you use an ISU port as an I2C master interface, you can't use the same port as an SPI or UART interface. 0-byte I2C reads are not supported. The following I2C settings are supported:

• 100 KHz, 400 KHz, and 1 MHz bus speeds.
• Custom timeout for operations.

I2S

Two blocks of five pins are multiplexed between GPIO and I2S. I2S is currently supported for M4 applications only.

ADC

The MT3620 contains a 12-bit ADC with 8 input channels. A block of eight pins is multiplexed between GPIO and the ADC. The ADC input channels and the GPIO pins GPIO41 through GPIO48 map to the same pins on the MT3260. However, if your application uses the ADC, then all 8 pins are allocated for use as ADC inputs and none of them can be used for GPIO.

ARM Cortex-M4F subsystems

The MT3620 includes two general-purpose ARM Cortex-M4F subsystems, each of which has a dedicated GPIO/UART block.

The MT3620 supports a default clock rate of 26 MHz. However, each M4 core can be independently configured to run at any clock rate between 1 MHz and 200 MHz by setting its HCLK_CK_CTRL register. The following code demonstrates one way to set the clock rate to 200 MHz:

        volatile unsigned int *hclk_ck_ctrl = (unsigned int *)0x2101000c;

        *hclk_ck_ctrl = 0x00040200;

The ARM Cortex-M4F subsystems can be programmed to support external interrupts. See Use external interrupts in real-time capable applications for details.

Application processor subsystem

The ARM Cortex-A7 subsystem runs a customer application along with the Microsoft-supplied Linux-based kernel, services, and libraries.

The service UART is dedicated to system functionality for the A7 subsystem. It is not available for customer application use.

The one-time programmable e-fuse block, for storing device specific information, cannot be used by customer applications.

Wi-Fi Subsystem

The Wi-Fi subsystem is currently IEEE 802.11 b/g/n compliant at both 2.4 GHz and 5 GHz.

Currently, Azure Sphere only supports WPA2, EAP-TLS, and open (no password) authentication.

See RF test tools for information about radio-frequency testing and calibration.

Power control

The MT3620 includes Power Down and Power Profile features to control power consumption. See Power Down considerations and Power Profile considerations for details.

Clocks and power sources

The main crystal can currently only be 26MHz. Crystal frequencies other than 26MHz are not currently supported in software.

Brownout detection

Brownout detection is not currently supported.

Hardware watchdog timers

The MTK3620 includes several watchdog timers:

• One watchdog timer dedicated for use by the Pluton security domain. This watchdog timer is not available for use by applications.
• One watchdog timer available to the application processor. The Azure Sphere OS uses this watchdog timer for system services. This watchdog timer is not available to applications.
• A watchdog timer for each of the real-time cores. These watchdog timers are available to real-time applications.

See Use a watchdog timer in an RTApp for more information.

SWD, SWO

Serial-wire debug (SWD, pins 98-99) is supported for M4 applications only. Serial-wire output (SWO, pin 100) is not currently supported. Debugging an A7 application is supported by a Microsoft-supplied gdb-based mechanism.

RAM and flash

The MT3620 includes approximately 5 MB RAM on-die, including 256 KiB in each I/O subsystem and 4 MB in the A7 application subsystem.

The MT3620 can be ordered with 16 MB of SPI flash memory.

For information about RAM and flash available for applications, see Memory available for applications.

Manufacturing test support

Documentation and utilities to support the integration of custom manufacturing test applications with factory processes are not yet available.

Pinout