Real-Time Data-Cache-Size Calculation Test (Windows Embedded CE 6.0)
1/6/2010
The purpose of the Real-time Data-Cache-Size Calculation test is to calculate the size of the L1 data cache while the Windows Embedded CE device is used. This is done by continuously reading the data from the cache. Determining the size of the L1 cache lets you minimize latencies in accessing memory that reduce L1 data cache misses.
Data caches take advantage of memory locale. This gives the illusion of a large, cheap memory that has the access time of fast, expensive memory. This memory hierarchy is designed to avoid latency in accessing data, to minimize gaps in access time among different kinds of memory, and to make the best use of CPU resources.
The following table shows the cache miss rates for different stride sizes when they read a 64 KB array, assuming an L1 data cache of 32 KB and a cache line of 32 bytes.
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Table 1 Cache miss rates for different stride sizes
| Slots by DWORD | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | |
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Stride |
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Cache Miss Rate |
8 DWORDs |
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1 |
4 DWORDs |
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½ |
2 DWORDs |
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¼ |
1 DWORD |
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⅛ |
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Note
One DWORD = 4 bytes
Data access is the final measure for evaluating the cache miss rate. To do this, allocate different arrays with different sizes, read data from those arrays into the cache by choosing different stride sizes, and then compare the cache access execution time for each. By searching for big jumps in access times, you can determine the size of the cache.
If the cache size is 32 KB, the test accesses an integer array that has sizes from 4 KB to 512 KB. In this case, the big jump occurs when the test accessed the 64 KB array. In theory, no miss should occur when accessing the 32 KB array, given a stride size of 4 bytes, and the running time can be only the hit time of "HitTime."
When the test accesses the 64 KB array with a different stride size, you can use the following formula to calculate the corresponding "MissTime" of accessing the 64 KB array with different stride sizes:
MISS_RATE*MissTime[64KB] + (1- MISS_RATE)*HitTime[32KB] = AccessTime[64KB]
In this formula, MISS_RATE is the miss rate for the specific stride size. See Table 1 for the corresponding miss rates. The AccessTime[64KB] is the total time to access the 64 KB array for the stride.
By comparing the miss times for the different data stride sizes, you can find the big jump for a specific stride size and therefore determine the size of the cache line.
In this Section
Prerequisites of the Real-Time Data-Cache-Size Calculation Test |
Specifies the hardware and software requirements for this test. |
Test Cases for the Real-Time Data-Cache-Size Calculation Test |
Describes the test cases for this test. |
Command-Line Parameters for the Real-Time Data-Cache-Size Calculation Test |
Describes the command-line parameters for this test. |
Describes how to run this test. |
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Troubleshooting the Real-Time Data-Cache-Size Calculation Test |
Provides troubleshooting and debugging information for the test. |