/QMRnnnn -Optimize for specific MIPS chip
These options cause the compiler to generate code optimized for a particular MIPS ISA, and allow microprocessor-specific inline assembly instructions. The compiler may then choose instructions or sequences of instructions specific to that particular processor, and produce an executable that is incompatible with any other processor.
The following table shows the implementation of /QMRX000 switches.
| Option | Equivalent to | Processor |
|---|---|---|
| /QMR3900 | -QMmips2 -D_M_MRX000=3900 | R3900 |
| /QMR4100 | -QMmips2 -D_M_MRX000=4100 | R4100 |
| /QMR4200 | -QMmips2 -QMFPE- -D_M_MRX000=4200 | R4200 |
| /QMR4300 | -QMmips2 -QMFPE- -D_M_MRX000=4300 | R4300 |
| /QMR5400 | -QMmips4 -QMFPE- -D_m_MRX000=5400 | R5400 |
Note These switches are mutually exclusive of each other and the /QMmips16 - Generate Code for MIPS16 ASE switch.
See Also
About Microprocessor Compilers | MIPS Guide | /QMmips16 - Generate Code for MIPS16 ASE
Last updated on Thursday, April 08, 2004
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