MIPS Microprocessor (Windows CE 5.0)
All MIPS interrupt service routines (ISRs) can be written in C. Any volatile registers can be used in accordance with the C calling convention without using save/restore. Specifically, a MIPS ISR can use registers a0 through a3, t0 through t7, v0, v1, and AT.
Use the following design principals when creating an OAL for a MIPS microprocessor:
The ISR must return by means of jra.
Implement a system-timer ISR that increments the variable CurMSec.
OEMInit needs to register the system-timer ISR.
Create the OAL function GetTickCount to return a value from the system timer.
The OEMIdle function takes a single parameter that is only used by the MIPS CPU.
This parameter is undefined for other CPUs. It is the base program status register (PSR) value and sets interrupts to be enabled. The following code example shows how OEMIdle is defined for the MIPS microprocessor.
void OEMIdle(DWORD dwIdleParam);Nested interrupts.
The MIPS kernel utilizes a structure that provides information about which nested interrupts are masked while the current interrupt is being handled. To gain access to this structure, the IntrPrio global variable must be declared in the OAL.
See Also
How to Develop an OEM Adaptation Layer | Microprocessor-specific Issues
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