OEMCacheRangeFlush Function Implementation
The Windows CE .NET kernel has replaced calls to FlushDCache, FlushICache and ClearTLB with calls to the OEMCacheRangeFlush function. OEMCacheRangeFlush has been customized for various CPU architectures and componentized into libraries in the CSP directory. These libraries must be included in order for your kernel to link correctly. The following table shows the libraries located in %_WINCEROOT%\Public\Common\Oak\CSP.
| CPU architecture | Library |
|---|---|
| MIPS | Csp_mips.lib |
| ARM\ARM720t | Csp_arm720t.lib |
| ARM\ARM920t | Csp_arm920t.lib |
| ARM\Common | Csp_arm.lib |
| ARM\SA11x0 | Csp_sa11x0.lib |
| ARM\XScale | Csp_xscale.lib |
| I486\OAL | I486oal.lib |
| SHX\SH3 | Csp_sh3.lib |
| SHX\SH4 | Csp_sh4.lib |
Note ARM builds typically link with one or more CSP libraries.
Some of the CSP routines reference global variables containing cache and TLB size information. Your platform must resolve these variables. You can further optimize such CSP implementations by hard-coding variables in a private implementation of OEMCacheRangeFlush in your platform.
If you want to modify or override CSP implementations of caching code, you must put the relevant source files in the Kernel\Buildexe directory and modify each of the source files in its subdirectories to build the file.
See Also
Cache Flush Routines | How to Develop an OEM Adaptation Layer | How to Migrate a Board Support Package to Windows CE .NET 4.2
Last updated on Wednesday, April 13, 2005
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