rm (Register Mask)

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The rm command modifies or displays the register display mask. This mask controls how registers are displayed by the r (Registers) command.

rm 
rm ? 
rm Mask

Parameters

?
Displays a list of possible Mask bits.

Mask
Specifies the mask to use when the debugger displays the registers. Mask is a sum of bits that indicate something about the register display. The meaning of the bits depends on the processor and the mode. For more information; see the tables in the following Remarks section.

Environment

Item Description
Modes User mode, kernel mode
Targets Live, crash dump
Platforms All

Remarks

The "m" in the command name must be a lowercase letter.

If you use rm with no parameters, the current value is displayed, along with an explanation about its bits.

To display the basic integer registers, you must set bit 0 (0x1) or bit 1 (0x2). By default, 0x1 is set for 32-bit targets and 0x2 is set for 64-bit targets. You cannot set these two bits at the same time--if you try to set both bits, 0x2 overrides 0x1.

You can override the default mask by using the r (Registers) command together with the M option.

The following Mask bits are supported for an x86-based processor or an x64-based processor.

Bit Value Description

0 1

0x1 0x2

Displays the basic integer registers. (Setting one or both of these bits has the same effect.)

2

0x4

Displays the floating-point registers.

3

0x8

Displays the segment registers.

4

0x10

Displays the MMX registers.

5

0x20

Displays the debug registers. In kernel mode, setting this bit also displays the CR4 register.

6

0x40

Displays the SSE XMM registers.

7

0x80

(Kernel mode only) Displays the control registers, for example CR0, CR2, CR3 and CR8.

8

0x100

(Kernel mode only) Displays the descriptor and task state registers.

9

0x200

Displays the AVX YMM registers in floating point.

10

0x400

Displays the AVX YMM registers in decimal integers.

11

0x800

Displays the AVX XMM registers in decimal integers.

12

0x1000

Displays the AVX-512 zmm0-zmm31 registers in floating point format.

13

0x2000

Displays the AVX-512 zm00-zmm31 registers in integer format.

14

0x4000

Displays the AVX-512 k0-k7 registers.

Examples

Enable the integer state and segment registers.

0: kd> rm 0x00a
0: kd> rm
Register output mask is a:
       2 - Integer state (64-bit)
       8 - Segment registers

Enable 0x1000 (Displays the AVX-512 zmm0-zmm31 registers in floating point format).

0: kd> rm 0x100a
0: kd> rm
Register output mask is 100a:
       2 - Integer state (64-bit)
       8 - Segment registers
    1000 - AVX-512 ZMM registers

Enable mask 0x2000 (Displays the AVX-512 zmm00-zmm31 registers in integer format).

0: kd> rm 0x200a
0: kd> rm
Register output mask is 200a:
       2 - Integer state (64-bit)
       8 - Segment registers
    2000 - AVX-512 ZMM Integer registers

Enable all AVX-512 register masks:

0: kd> rm 0x700a
0: kd> rm
Register output mask is 700a:
       2 - Integer state (64-bit)
       8 - Segment registers
    1000 - AVX-512 ZMM registers
    2000 - AVX-512 ZMM Integer registers
    4000 - AVX-512 Opmask registers

If you try and set a register mask on hardware that does not support it, the invalid bits of the register mask will be ignored.

kd> rm 0x100a
Ignored invalid bits 1000
kd> rm
Register output mask is a:
      2 - Integer state (64-bit)
       8 - Segment registers