SH3-DSP Status Registers

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The following table describes the layout of the SH3-DSP Status Register.

Bit Name
0 T
1 S
2 RF0
3 RF1
4 I0
5 I1
6 I2
7 I3
8 Q
9 M
10 DMX
11 DMY
12 DSP
13

15

 0 –

0
16

27

RC
28 BL
29 RB
30 MD
31 0

The following table describes the functionality of the different bits in the Status Register.

SR Bit Function
MD Processor operation mode:
  • MD = 1 Privileged mode
  • MD = 0 User mode
RB Register bank bit; used to define the general registers in privileged mode.
  • RB = 1 R0_BANK1 to R7_BANK1 are used as general registers, R0_BANK0 to R7_BANK0 accessed by LDC/STC instructions
  • RB = 0 R0_BANK0 to R7_BANK0 are used as general registers, R0_BANK1 to R7_BANK1 accessed by LDC/STC instructions
BL Block bit; used to mask exception in privileged mode.
  • BL = 1 Interrupts are masked and not accepted
  • BL = 0 Interrupts are accepted
RC [11:0] 12-bit repeat counter
DSP DSP operation mode
  • DSP = 1 DSP instructions are enabled.
  • DSP = 0 All DSP instructions are treated as illegal instructions; only SH-3 instructions are supported.
DMY Modulo addressing enable for Y side
DMX Modulo addressing enable for X side
Q, M Used by DIV0U/S and DIV1 instructions.
I [3:0] 4-bit field indicating the interrupt-request mask level.
RF [1:0] Used for repeat control.
S bit Used by the MAC instructions and DSP data.
T bit The MOVT, CMP/cond, TAS.TST, BT, BF, SETT, CLRT, and DT instructions use the T bit to indicate true or false.

The ADDV/C, SUBV/C, DIV0U/S, DIV1, NEGC, SHAR/L, SHLR/L, ROTR/L, and ROTCR/L instructions use the T bit to indicate a carry, borrow, overflow, or underflow.
Reserved bits Always read as 0, and should always be written with 0.

See Also

SH3-DSP Registers | SH3-DSP General Registers | SH3-DSP Control Registers | RS, RE, and ME Control Registers | SH3-DSP System Registers | DSP Unit Registers

 Last updated on Thursday, April 08, 2004

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