Instruction Token

An instruction token informs the driver of a specific operation to perform and is composed of the following bits:

Bits

[15:00] Bits 0 through 15 indicate an operation code. D3DSIO_* is an example of an operation code, where * represents the instruction. For example, the following code snippet shows an ADD instruction:

// D3DSIO_ADD d, s1, s2

[23:16] Bits 16 through 23 indicate specific controls related to the operation code.

[27:24] For pixel and vertex shader versions earlier than 2_0, bits 24 through 27 are reserved and set to 0x0.

For pixel and vertex shader versions 2_0 and later, bits 24 through 27 specify the size in DWORDs of the instruction excluding the instruction token itself (that is, the number of tokens that comprise the instruction excluding the instruction token).

[28] For pixel and vertex shader versions earlier than 2_0, bit 28 is reserved and set to 0x0.

For pixel and vertex shader versions 2_0 and later, bit 28 indicates whether the instruction is predicated (that is, contains an extra predicate source token at the end of the shader code. If this bit is set to 0x1, the instruction is predicated.

[29] Reserved. This value is set to 0x0.

[30] For pixel shader versions earlier than 2_0, bit 30 is the co-issue bit. If set to 1, execute this instruction with previous instructions; otherwise, execute separately.

For pixel shader version 2_0 and later and all vertex shader versions, bit 30 is reserved and set to 0x0.

[31] Bit 31 is zero (0x0).

Comments

See the Pixel Shader Reference and Vertex Shader Reference in the latest DirectX SDK documentation for more information about operations that can be specified in bits 0 through 15 of instruction tokens.

After the DirectX3D runtime receives shader code from an application, the runtime validates the code before passing the code to the driver. Typically, the runtime prefixes assembler instructions with "D3DSIO_" to create the operation code. For example, the following assembler instructions correspond to kernel-mode operations:

Note that in all vertex shader versions, the sub assembler instruction is implemented as a D3DSIO_ADD operation with the source modifier (bits 27:24) of the second source set to negate (0x1).

The tex and texcoord instructions apply to pixel shader versions 1_0 through 1_3; each instruction has one destination parameter associated with it.

The texld and texcrd instructions are new to pixel shader version 1_4 and later; each instruction has both destination and source parameters associated with it.

The runtime converts the tex and texld assembler instructions to the D3DSIO_TEX kernel-mode operation. The runtime converts the texcoord and texcrd assembler instructions to the D3DSIO_TEXCOORD kernel-mode operation. Drivers first verify the pixel shader version of the shader code and then process the instructions accordingly. For example, if a driver verifies that it received version 1_4 pixel shader code with a D3DSIO_TEX operation, the driver determines that destination and source parameters follow the instruction token.

Requirements

Available in Windows Vista and later versions of the Windows operating systems.