Vertex Shader Differences
Instruction Slots
Each version supports a differing number of maximum instruction slots.
| Version | Maximum number of instruction slots |
|---|---|
| vs_1_1 | 128 |
| vs_2_0 | 256 |
| vs_2_x | 256 |
| vs_3_0 | 512 minimum, and up to the number of slots in D3DCAPS9.MaxVertexShader30InstructionSlots. See D3DCAPS9. |
For information about the limitations of software shaders, see Software Shaders.
Flow Control Nesting Limits
vs_1_1 Features
New instructions:
New registers:
See Registers - vs_1_1.
vs_2_0 Features
New features:
- Static flow control
- All four components of the Address Register (a0) are available.
New instructions:
- Setup instructions - defb - vs, defi - vs
- Arithmetic instructions - abs - vs, crs - vs, lrp - vs, mova - vs, nrm - vs, pow - vs, sgn - vs, sincos - vs
- Static flow control instructions - call - vs, callnz bool - vs, else - vs, endif - vs, endloop - vs, endrep - vs, if bool - vs, label - vs, loop - vs, rep - vs, ret - vs
New registers:
vs_2_x Features
New features (D3DCAPS9.VS20Caps):
- Dynamic flow control
- Nesting for dynamic and static flow control instructions
- Number of Temporary Registers (r#) increased
- Predication
New Instructions:
- Dynamic flow control instructions - break - vs, break_comp - vs, breakp - vs, callnz pred - vs, if_comp - vs, if pred - vs, setp_comp - vs
New registers:
- Predicate Register (p0)
vs_3_0 Features
New features :
- Texture lookup
- Indexable Output Registers (o#)
- Number of Temporary Registers (r#) increased to 32
New instructions:
- Setup instruction - dcl_samplerType (sm3 - vs asm)
- Texture instruction - texldl - vs
New registers:
Related topics